1. Field of the Invention
The present invention relates to semiconductor memory devices. More particularly, the present invention relates to a new static CMOS pullup cell, which is fast and consumes less current than a conventional pullup.
2. The Prior Art
Pulldown circuits comprising a plurality of N-Channel MOS transistors and a P-Channel dual are well known in the art. A pullup circuit may be used in place of the P-Channel dual. Such pullup circuits are normally designed for speed, although a tradeoff between speed and current tradeoff may sometimes be made for certain applications where reads are infrequent, and read-time isn't critical. Unlike the P-Channel dual it replaces, which is off (i.e., no current path from V.sub.DD to output) when the pulldown device(s) is on, the pullup circuit is on for some, if not all, of the time during which the pulldown device(s) is on. This operating mode results in static current or a large switching current consumption.
Static current flow and large switching currents may be tolerated in certain applications. However, there are applications where reduction or elimination of static current flow and reduction of large switching currents would be desirable.
It is an object of the present invention to provide a new static CMOS pullup cell, which is faster than a comparably-sized prior art pullup with feedback and which consumes less current than such a pullup.
It is a further object of the present invention to provide a pullup which, unlike prior art constant-current pullup circuits, consumes negligible static current and is less sensitive to process variation than either constant-current or feedback pullups.
Yet another object of the present invention is to provide a pullup which uses the same type (enhancement) MOS transistors as prior art pullups and can be fabricated using the existing CMOS processes without need to alter the processes.